C868 Datasheet, PDF (21/82 Pages) Infineon Technologies AG – 8-Bit Single-Chip Microcontroller

C868
Clock system
The C868 clock system consist of the on-chip oscillator, PLL and multiplexer stage. The
programmable Slow Down Divider (SDD) divides the PLL output clock frequency by a
factor of 1...32 which is specified via CMCON.REL. The system clock is switched from
the PLL output to the output from the SDD when slowdown mode is selected.
XTAL1
XTAL2
On-Chip
Osc
PLL
f_{OSC clkin}
clkout ^fPLL
SDD
MUX
system
clock (f_SYS)
Figure 11 Block Diagram of the Clock Generation
Data Sheet
21
V 1.0, 2003-05