TDA5250D2_07 Datasheet, PDF (64/94 Pages) Infineon Technologies AG – ASK/FSK 868MHz Wireless Transceiver

TDA5250 D2
Version 1.7
Application
1300
ADC
1200
1100
1000
900
800
700
600
500
high gain
400
low gain
300
200
100
0
-120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20
RF /dBm
Figure 3-24 Typ. RSSI Level (Eval Board) @3V
RSSI.wmf
3.6
Data Slicer - Slicing Level
The data slicer is an analog-to-digital converter. It is necessary to generate a threshold value for the
negative comparator input (data slicer). The TDA5250 offers an RC integrator and a peak detector
which can be selected via logic. Independent of the choice, the peak detector outputs are always
active.
3.6.1 RC Integrator
Table 3-12 Sub Address 00H: CONFIG
Bit
Function
Description
Default
SET
D15
SLICER
0= LP, 1= Peak Detector
0
0
Necessary external component (Pin14): C_SLC
This integrator generates the mean value of the data filter output. For a stable threshold value, the
cut-off frequency has to be lower than the lowest signal frequency. The cutoff frequency results from
the internal resistance R=100kΩ and the external capacitor C_SLC on Pin14.
Cut-off frequency:
{ } f
cut − off
=
2π
1
⋅100 kΩ ⋅C_SLC
< Min
f
Signal
Component calculation: (rule of thumb)
T_L – longest period of no signal change
C
SLC
≥ ^3⋅TL
100 k Ω
[3 – 30]
[3 – 31]
Data Sheet
64
2007-02-26