TDA5250D2_07 Datasheet, PDF (29/94 Pages) Infineon Technologies AG – ASK/FSK 868MHz Wireless Transceiver

TDA5250 D2
Version 1.7
Functional Description
Subaddress Organization
Table 2-16
MSB
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
Sub Addresses of Data Registers Write
LSB HEX
Function
Description
0 0 0 0 0 00h
CONFIG
General definition of status bits
0 0 0 0 1 01h
FSK
Values for FSK-shift
0 0 0 1 0 02h XTAL_TUNING
Nominal frequency
0 0 0 1 1 03h
LPF
I/Q and data filter cutoff frequencies
0 0 1 0 0 04h
ON_TIME
ON time of wakeup counter
0 0 1 0 1 05h OFF_TIME
OFF time of wakeup counter
0 0 1 1 0 06h COUNT_TH1
Lower threshold of window counter
0 0 1 1 1 07h COUNT_TH2
Higher threshold of window counter
0 1 0 0 0 08h RSSI_TH3
Threshold for RSSI signal
0 1 1 0 1 0Dh
CLK_DIV
Configuration and Ratio of clock divider
0 1 1 1 0 0Eh XTAL_CONFIG
XTAL configuration
0 1 1 1 1 0Fh BLOCK_PD
Building Blocks Power Down
Bit Length
16
16
16
8
16
16
16
16
8
8
8
16
Table 2-17
MSB
1 00
1 00
Sub Addresses of Data Registers Read
LSB HEX
Function
Description
0 0 0 0 0 80h
STATUS
Results of comparison: ADC & WINDOW
0 0 0 0 1 81h
ADC
ADC data out
Bit Length
8
8
Data Byte Specification
Table 2-18 Sub Address 00H: CONFIG
Bit
Function
Description
D15
SLICER
0= Lowpass, 1= Peak Detector
D14
ALL_PD
0= normal operation, 1= all Power down
D13
TESTMODE
0= normal operation, 1=Testmode
D12
CONTROL
0= RX/TX and ASK/FSK external controlled, 1= Register controlled
D11
ASK_NFSK
0= FSK, 1=ASK
D10
RX_NTX
0= TX, 1=RX
D9
CLK_EN
0= CLK off during power down, 1= always CLK on, ever in PD
D8
RX_DATA_INV
0= no Data inversion, 1= Data inversion
D7
D_OUT
0= Data out if valid, 1= always Data out
D6
ADC_MODE
0= one shot, 1= continuous
D5
F_COUNT_MODE
0= one shot, 1= continuous
D4
LNA_GAIN
0= low gain, 1= high gain
D3
EN_RX
0= disable receiver, 1= enable receiver (in self polling and timer mode) *
D2
MODE_2
0= slave mode, 1= timer mode
D1
MODE_1
0= slave or timer mode, 1= self polling mode
D0
PA_PWR
0= low TX Power, 1= high TX Power
Default
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
1
Note D3: Function is only active in selfpolling and timer mode. When D3 is set to LOW the RX path
is not enabled if PwdDD pin is set to LOW. A delayed setting of D3 results in a delayed power ON
of the RX building blocks.
Data Sheet
29
2007-02-26