TDA5250D2_07 Datasheet, PDF (37/94 Pages) Infineon Technologies AG – ASK/FSK 868MHz Wireless Transceiver

TDA5250 D2
Version 1.7
Functional Description
Table 2-32 CLK_DIV Output Selection
D5
D4
Output
0
0
Output from Divider (default)
0
1
18.089MHz
1
0
32kHz
1
1
Window Count Complete
Note: Data are valid 500 µs after the crystal oscillator is enabled (see Figure 2-15 and Figure 2-
16, tCLKSU).
Table 2-33 CLK_DIV Setting
D3 D2 D1 D0 Total Divider Ratio
0
0
0
0
2
0
0
0
1
4
0
0
1
0
6
0
0
1
1
8
0
1
0
0
10
0
1
0
1
12
0
1
1
0
14
0
1
1
1
16
1
0
0
0
18
1
0
0
1
20
1
0
1
0
22
1
0
1
1
24
1
1
0
0
26
1
1
0
1
28
1
1
1
0
30
1
1
1
1
32
Output Frequency [MHz]
9,0
4,5
3,0
2,25
1,80
1,50
1,28
1,125
1,00 (default)
0,90
0,82
0,75
0,69
0,64
0,60
0,56
Note: As long as default settings are used, there is no clock available at the clock output during
Power Down. It is possible to enable the clock during Power Down by setting CLK_EN (Bit D9) in
the Config Register (00H) to HIGH.
2.4.20 RSSI and Supply Voltage Measurement
The input of the 6Bit-ADC can be switched between two different sources: the RSSI voltage (default
setting) or a resistor network dividing the Vcc voltage by 5.
Table 2-34 Source for 6Bit-ADC Selection (Register 08H)
SELECT
Input for 6Bit-ADC
0
Vcc / 5
1
RSSI (default)
Data Sheet
37
2007-02-26