TDA5250D2_07 Datasheet, PDF (24/94 Pages) Infineon Technologies AG – ASK/FSK 868MHz Wireless Transceiver

TDA5250 D2
Version 1.7
Functional Description
The DATA VALID DETECTOR contains a frequency window counter and an RSSI threshold
comparator. The window counter uses the incoming data signal from the data slicer as the gating
signal and the crystal oscillator frequency as the timebase to determine the actual datarate. The
result is compared with the expected datarate.
The threshold comparator compares the actual RSSI level with the expected RSSI level.
If both conditions are true the PwdDD pin is set to LOW in self polling mode as you can see in
Section 2.4.16. This signal can be used as an interrupt for an external µP. Because the PwdDD
pin is bidirectional and open drain driven by an internal pull-up resistor it is possible to apply an
external LOW thus enabling the device.
2.4.15 Bus Interface and Register Definition
The TDA5250 supports the I²C bus protocol (2 wire) and a 3-wire bus protocol. Operation is
selectable by the BusMode pin (pin 2) as shown in the following table. All bus pins (BusData,
BusCLK, EN, BusMode) have a Schmitt-triggered input stage. The BusData pin is bidirectional
where the output is open drain driven by an internal 15kΩ pull up resistor.
Table 2-6 Bus Interface Format
Function
I²C Mode
BusMode
Low
3-wire Mode
High
EN
High= inactive,
Low= active
BusCLK
Clock input
BusData
Data in/out
BusData
16
BusCLK
17
EN
24
BusMode
2
I²C / 3-wire INTERNAL BUS
INTERFACE
11100000
CHIP ADDRESS
Figure 2-7 Bus Interface
i2c_3w_bus.wmf
Note: The Interface is able to access the internal registers at any time, even in POWER DOWN
mode. There is no internal clock necessary for Interface operation.
I²C Bus Mode
In this mode the BusMode pin (pin 2) = LOW and the EN pin (pin 24) = LOW.
Data Sheet
24
2007-02-26