TDA5250D2_07 Datasheet, PDF (23/94 Pages) Infineon Technologies AG – ASK/FSK 868MHz Wireless Transceiver

TDA5250 D2
Version 1.7
Functional Description
Table 2-5
PwdDD Pin Operating States
PwdDD
VDD
Ground/VSS
Operating State
Powerdown Mode
Device On
2.4.14 Timing and Data Control Unit
The timing and data control unit contains a wake-up logic unit, an I²C/3-wire microcontroller
interface, a “data valid” detection unit and a set of configuration registers as shown in the
subsequent figure.
I²C / 3Wire
INTERFACE
INTERNAL BUS
18 MHz
XTAL-Osz.
RSSI ^{6 Bit}
ADC
RX DATA
DATA VALID
DETECTOR
AMPLITUDE
threshold TH3
FREQUENCY
window
TH1<T_GATE<TH2
WAKEUP
LOGIC
32kHz
RC-Osz.
FSK DATA
ASK DATA
BLOCK ENABLE
ASK / FSK
RX / TX
CONTROL
LOGIC
POWER ON
SEQUENCER
CLKDiv
PwdDD
Data
AskFsk
RxTx
Reset
logic.wmf
Figure 2-6 Timing and Data Control Unit
The I²C / 3-wire Bus Interface gives an external microcontroller full control over important system
parameters at any time.
It is possible to set the device in three different modes: Slave Mode, Self Polling Mode and Timer
Mode. This is done by a state machine which is implemented in the WAKEUP LOGIC unit. A
detailed description is given in Section 2.4.16.
Data Sheet
23
2007-02-26