HYS64D16020GD Datasheet, PDF (6/22 Pages) Infineon Technologies AG – Unbuffered DDR SDRAM SO Modules

HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Overview
1
Overview
1.1
Features
• 200-pin Unbuffered 8-Byte Dual-In-Line DDR SDRAM non-parity Small Outline Modules
• One rank 16M x 64 organization
• JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM)
• Single + 2.5 V (± 0.2 V) power supply
• Built with 128 Mbit DDR SDRAMs organised as x 16 in 66-Lead TSOPII packages
• Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• Serial Presence Detect with E²PROM
• JEDEC standard form factor: 67.60 mm × 31.75 mm × 3.00 / 3.80 mm
• JEDEC standard reference layout Raw Card A
• Gold plated contacts
Table 1 Performance -8/-7
Part Number Speed Code
Speed Grade
max. Clock Frequency
Component
Module
@CL2.5
@CL2
f_CK2.5
f_CK2
–7
DDR266A
PC2100-2033
143
133
–8
DDR200
PC1600-2022
125
100
Unit
—
—
MHz
MHz
1.2
Description
The HYS64/72D16000GU and HYS64/72D32020GU are industry standard 184-pin 8-byte Dual in-line Memory
Modules (DIMMs) organized as 16M x 64 and 32M × 64 for non-parity and 16M x 72 and 32M x 72 for ECC main
memory applications. The memory array is designed with 128Mbit Double Data Rate Synchronous DRAMs. A
variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based
on a serial E²PROM device using the 2-pin I²C protocol. The first 128 bytes are programmed with configuration
data and the second 128 bytes are available to the customer.
Data Sheet
6
Rev. 1.02, 2004-01
11042003-YIV7-VK6M