HYS64D16020GD Datasheet, PDF (19/22 Pages) Infineon Technologies AG – Unbuffered DDR SDRAM SO Modules

4
SPD Contents
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
SPD Contents
Table 11 SPD Codes for PC2100 & PC1600
Byte#
Description
0
Number of SPD Bytes
128
1
Total Bytes in Serial PD
256
2
Memory Type
DDR-SDRAM
3
Number of Row Addresses
12
4
Number of Column Addresses 9
5
Number of DIMM Ranks
2
6
Module Data Width
×64
7
Module Data Width (cont’d)
0
8
Module Interface Levels
SSTL_2.5
9
SDRAM Cycle Time at CL = 2.5 7 ns/8 ns
10
Access Time from Clock at
0.75 ns/0.8 ns
CL = 2.5
11
DIMM config
non-ECC/ECC
12
Refresh Rate/Type
Self-Refresh 15.6 ms
13
SDRAM Width, Primary
×16
14
Error Checking SDRAM Data na
Witdh
15
Minimum Clock Delay for Back- t_CCD = 1 CLK
to-Back Random Column
Address
16
Burst Length Supported
2, 4 & 8
17
Number of SDRAM Ranks
4
18
Supported CAS Latencies
CAS latency = 2 & 2.5
19
CS Latencies
CS latency = 0
20
WE Latencies
Write latency = 1
21
SDRAM DIMM Module Attributes unbuffered
22
SDRAM Device Attributes:
Concurrent Auto Precharge,
General
weak driver
23
Min. Clock Cycle Time at CAS 7.5 ns/10 ns
Latency = 2
24
Access Time from Clock for
0.75 ns/0.8 ns
CL = 2
25
Minimum Clock Cycle Time for not supported
CL = 1.5
26
Access Time from Clock at
not supported
CL = 1.5
27
Minimum Row Precharge Time 20 ns
128MB
x64
2ranks
–7
HEX.
80
08
07
0C
09
02
40
00
04
70
75
00
80
10
00
01
0E
04
0C
01
02
20
C1
75
75
00
00
50
128MB
x64
2ranks
–8
HEX.
80
08
07
0C
09
02
40
00
04
80
80
02
80
10
00
01
0E
04
0C
01
02
20
C1
A0
80
00
00
50
Data Sheet
19
Rev. 1.02, 2004-01
11042003-YIV7-VK6M