HYS64D16020GD Datasheet, PDF (18/22 Pages) Infineon Technologies AG – Unbuffered DDR SDRAM SO Modules

HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Electrical Characteristics
7) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t_DQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between V_OH(ac) and V_OL(ac).
11) CAS Latency 1.5 operation is supported on DDR200 devices only
12) t_RPRES is defined for CL = 1.5 operation only
13) For each of the terms, if not already an integer, round to the next highest integer. t_CK is equal to the actual system clock
cycle time.
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
18
Rev. 1.02, 2004-01
11042003-YIV7-VK6M