HYS64D16020GD Datasheet, PDF (10/22 Pages) Infineon Technologies AG – Unbuffered DDR SDRAM SO Modules

HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Pin Configuration
Table 4 Pin Configuration (cont’d)
Frontside
PIN# Symbol
PIN# Symbol
40
DQ27
41
A2
85
V_DD
86
DQS7
42
V_SS
43
A1
87
DQ58
88
DQ59
44
NC / CB0
45
NC / CB1
89
V_SS
90
NC
46
V_DD
47
NC / DQS8
91
SDA
92
SCL
Backside
PIN# Symbol
132
V_SS
133 DQ31
134 NC / CB4
135 NC / CB5
136
V_DDQ
137 CK0
138
CK0
139
V_SS
PIN#
177
178
179
180
181
182
183
184
Symbol
DM7/DQS16
DQ62
DQ63
V_DDQ
SA0
SA1
SA2
V_DDSPD
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“not connected”) on ×64 organised non-ECC
modules.
Table 5 Address Format
Density
Organization
Memory SDRAMs
Ranks
# of
SDRAMs
SDRAM # of
density row/rank/
columns
bits
Refresh
Period
Interval
128 MB 16M × 64
2
8M × 16 8
128Mbit 12/2/9
4K
64 ms 15.6 µs
Note: Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84, 89 and 91 are reserved for x72 variants of this module and are
not used on the x64 versions. Pin 86 is reserved for a registered variant of this module and is not used on
the unbuffered version
front side
Figure 1 Pin Configuration
back side
Data Sheet
10
Rev. 1.02, 2004-01
11042003-YIV7-VK6M