HYB39S64160BT-8 Datasheet, PDF (49/53 Pages) Infineon Technologies AG – 64-MBit Synchronous DRAM

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20. Full Page Read Cycle
20.1 CAS Latency = 2
HYB39S64400/800/160BT(L)
64MBit Synchronous DRAM
Burst Length = Full Page, CAS Latency = 2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t _CK2
CKE High
CS
RAS
CAS
WE
BS
AP
RAx
RBx
RBy
Addr.
RAx
CAx
RBx
CBx
DQM
RBy
t _RP
Hi-Z
DQ
Ax Ax+1 Ax+ 2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Burst Stop Precharge
Command Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
Activate
Command
Bank B
SPT03929
Semiconductor Group
48