HYB39S64160BT-8 Datasheet, PDF (24/53 Pages) Infineon Technologies AG – 64-MBit Synchronous DRAM

3. Read Interrupted by a Read
HYB39S64400/800/160BT(L)
64MBit Synchronous DRAM
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command Read A Read B NOP NOP NOP NOP NOP NOP NOP
CAS
latency = 2
t _CK2, DQ’s
CAS
latency = 3
t _CK3, DQ’s
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
SPT03713
4. Read to Write Intrerval
4.1 Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0
T1
T2
T3
T4
T5
CLK
Minimum delay between the Read and Write
Commands = 4 + 1 = 5 cycles
DQMx
t _DQZ
Command NOP Read A NOP NOP NOP NOP
T6
T7
T8
Write latency t _DQW of DQMx
Write B NOP NOP
DQ’s
"H" or "L"
DOUT A0
DIN B0
Must be Hi-Z before
the Write Command
DIN B1
DIN B2
SPT03787
Semiconductor Group
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