HYB39S64160BT-8 Datasheet, PDF (23/53 Pages) Infineon Technologies AG – 64-MBit Synchronous DRAM

1. Bank Activate Command Cycle
HYB39S64400/800/160BT(L)
64MBit Synchronous DRAM
(CAS latency = 3)
T0
T1
T
T
CLK
Address
Bank B
Row Addr.
Command
Bank B
Activate
t _RCD
NOP NOP
"H" or "L"
Bank B
Col. Addr.
Write B
with Auto
Precharge
t _RC
T
T
T
Bank A
Row Addr.
t _RRD
Bank A
Activate
NOP
Bank B
Row Addr.
Bank B
Activate
SPT03784
2. Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command Read A NOP NOP NOP NOP NOP NOP NOP NOP
CAS
latency = 2
t _CK2, DQ’s
CAS
latency = 3
t _CK3, DQ’s
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
SPT03712
Semiconductor Group
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