HYB39S64160BT-8 Datasheet, PDF (19/53 Pages) Infineon Technologies AG – 64-MBit Synchronous DRAM

HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Notes
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests have V_IL = 0.4 V and V_IH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between V_IH and V_IL. All AC measurements assume
t_T = 1 ns with the AC output load circuit shown in figure below. Specified t_AC and t_OH parameters
are measured with a 50 pF only, without any resistive termination and with a input signal of 1V /
ns edge rate between 0.8 V and 2.0 V.
CLOCK
t _CL
t _SETUP
t _HOLD
INPUT
OUTPUT
1.4 V
t_AC
t _LZ
t _CH
2.4 V
0.4 V
t_T
t_AC
t _OH
1.4 V
t _HZ
SPT03404
I/O
50 pF
Measurement conditions for
t_AC and t_OH
3. If clock rising time is longer than 1 ns, a time (t_T/2 − 0.5) ns has to be added to this parameter.
4. If t_T is longer than 1 ns, a time (t_T − 1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency
of the clock, as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole
number)
6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to t_RC is satisfied
once the Self Refresh Exit command is registered.
Data Book
19
12.99