C166SV2 Datasheet, PDF (41/438 Pages) Infineon Technologies AG – 16-Bit Microcontroller

User Manual
C166S V2
Central Processing Unit
PSW
Processor Status Word
15 14 13 12 11 10
ILVL
rwh
IEN
HLD
EN
rw rw
SFRb
Reset Value: 0000_H
9876543210
BANK
rwh
MUL
USR1 USR0 _IP
E
Z
V
C
N
rwh rwh rwh rwh rwh rwh rwh rwh
Field
BANK
Bits Type Description
9-8 rwh Reserved for register file bank selection
00 Global register bank
01 Reserved
10 Local register bank 1
11 Local register bank 2
In case of an interrupt service, the bank switch is automatically executed by updating the
PSW. The Interrupt Controller (ITC) configuration decides which register bank will be
selected. By executing a RETI instruction, the BANK bit field of the PSW will
automatically be restored and the context will switched to the original register bank.
global
Bank
Execution
Task A
Interrupt of Task B
recognized
local
Bank
Execution
Task B
Execution of
RETI
global
Bank
Execution
Task A
Figure 2-11 Context Switch by Changing the Physical Register Bank
After a switch to a local register bank, the new bank is immediately available. After
switching to the global register bank, the cached memory-mapped GPRs must be valid
before any further instructions can be executed. If the global register bank is not valid at
this time (in case if the context switch process has been interrupted), the cache
validation process is repeated automatically. For further explanation, please refer to
Section 2.4.3.2.
Note: The switch between the three physical register banks of the register file can also
be executed by writing to the BANK bitfield of the PSW. Because of pipeline
dependencies an explicit change of the PSW must cancel the pipeline.
User Manual
2-41
V 1.7, 2001-01