C166SV2 Datasheet, PDF (113/438 Pages) Infineon Technologies AG – 16-Bit Microcontroller

User Manual
C166S V2
Instruction Pipeline
• The third class are CSFRs which affect the whole CPU or the pipeline before the
Memory stage. The CPU-SFRs CPUCON1, CP, SP, STKUN, STKOV, VECSEG,
TFR, and PSW affect the overall CPU functioning while the C-SFRs IDX0, IDX1, QX1,
QX0, DPP0, DPP1, DPP2 and DPP3 only affect the Decode, Address, and Memory
stage when they are modified explicitly.
If this kind of CSFR has been modified, the pipeline behavior depends on the
instruction and addressing modes used to modify the CSFR.
– In the case of modification of these CSFRs by “POP CSFR” or by instructions using
the reg,#data16 addressing mode, a special mechanism is implemented to improve
performance during the initialization.
For further explanation, the instruction which modifies the CSFR can be called
“instruction_modify_CSFR”. This special case is detected in the Decode stage
when the instruction_modify_CSFR enters the processing pipeline. Further on,
instructions described in the following list are held in the decode stage. All other
instructions are not held.
- Instructions using long addressing mode (mem)
- Instructions using indirect addressing modes ([R_w], ]R_w+]......), except JMPI and
CALLI
- ENWDT, DISWDT, EINIT
- All CoXXX instructions
If the CPUCON1, CP, SP, STKUN, STKOV, VECSEG, TFR, or the PSW are
modified and the instruction_modify_CSFR reaches the execute stage, the pipeline
is canceled. The modification affects the entire pipeline and the instruction prefetch.
A clean cancel and restart mechanism is required to guarantee a correct instruction
flow. In case of modification of IDX0, IDX1, QX1, QX0, DPP0, DPP1, DPP2 or
DPP3 only the Decode, Address, and Memory stages are affected and the pipeline
must not be canceled. The modification does not affect the instructions in the
Address, Memory stage because they are not using this resource. Other kinds of
instructions are held in the Decode stage until the CSFR is modified.
The following example shows a case in which the pipeline is stalled. The instruction
MOV R6,R1 after the MOV IDX1,#12 instruction which modifies the CSFR will be
held in Decode Stage until the IDX1 register is updated. The next example shows
an optimized initialization routine.
User Manual
4-113
V 1.7, 2001-01