C166SV2 Datasheet, PDF (10/438 Pages) Infineon Technologies AG – 16-Bit Microcontroller

User Manual
C166S V2
Introduction
– Nearly all instructions executed in one CPU clock cycle
– Enhanced boolean bit manipulation facilities
– Zero cycle jump execution
– Additional instructions to support High Level Language (HLL) and operating systems
– Register-based design with multiple variable register banks
– Two additional fast register banks
– General purpose register architecture
– 16 General-purpose registers (GPRs) for byte operands
– 16 General-purpose registers (GPRs) for integer operands
– Overlapping 8-bit and 16-bit registers
– Opcode fully upward compatible with C166 family
– Variable stack with automatic stack overflow/underflow detection
– High performance branch-, call- and loop processing
– Multiply and accumulate instructions (MAC) executed in one CPU clock cycle
– Extremely short interrupt response time
– "Fast interrupt" and "Fast context switch" features
– Peripheral bus (PDBUS+) with bit protection
1.2
System Description
The basic C166S V2 System consists of the following main units:
• C166S V2 CPU
• On-Chip Data- and Code-Memories
• Data Management Unit (DMU)
• Program Management Unit (PMU)
• Interrupt and Peripheral Event Controller (PEC) Controller
• OCDS and JTAG-Interface
• External Bus Controller (EBC)
• System Control Unit (SCU)
• Clock Generation Unit (CGU)
The powerful C166S V2 core, the peripherals, and the internal memories of the
C166S V2 microcontroller are connected to various busses:
• 16-bit high performance system bus
• 16-bit enhanced peripheral bus (PDBUS+)
• 64-bit internal program memory bus
• 16-bit data memory bus
User Manual
1-10
V 1.7, 2001-01