C166SV2 Datasheet, PDF (21/438 Pages) Infineon Technologies AG – 16-Bit Microcontroller

User Manual
C166S V2
Central Processing Unit
caddr: Specifies an absolute 16-bit code address within the current segment.
Branches MAY NOT be taken to odd code addresses. Therefore, the least
significant bit of ’caddr’ is not used.
rel: This mnemonic represents an 8-bit signed word offset address relative to the
current Instruction Pointer contents, which points to the instruction after the
branch instruction. Depending on the offset address range, both forward (’rel’=
00_H to 7F_H) and backward (’rel’= 80_H to FF_H) branches are possible. The
branch instruction itself is repeatedly executed, when ’rel’ = ’-1’ (FF_H) for a
word-sized branch instruction, or ’rel’ = ’-2’ (FE_H) for a double-word-sized
branch instruction.
[Rw]:
In this case, the 16-bit branch target instruction address is determined indi-
rectly by the contents of a word GPR. In contrast to indirect data addresses,
indirectly specified code addresses are NOT calculated via additional pointer
registers (eg. DPP registers). Branches MAY NOT be taken to odd code
addresses. Therefore, the least significant bit of ’caddr’ is not used.
seg:
Specifies an absolute code segment number. The C166S V2 CPU supports
256 different code segments, so only the eight lower bits (respectively) of the
’seg’ operand value are used to update the CSP register.
#trap7: Specifies a particular interrupt or trap number for branching to the correspond-
ing interrupt or trap service routine via a jump vector table. Trap numbers from
00_H to 7F_H can be specified to access any double word code location within
the address range xx’0000_H...xx’15D4_H (depending of VECSC) in the selected
code segment (see VECSEG, i.e. the interrupt jump vector table), please refer
to Section 5.1.4.
User Manual
2-21
V 1.7, 2001-01