C166SV2 Datasheet, PDF (146/438 Pages) Infineon Technologies AG – 16-Bit Microcontroller

User Manual
C166S V2
Interrupt and Exception Handling
PECSEGx
SRCSEGx DSTSEGx
15
87
0
SRCPx
SRCPx
15
0
DSTPx
DSTPx
15
0
Source Pointer
23
16 15
Destination Pointer
0
23
16 15
0
Segment Address
Segment Offset
Segment Address
Segment Offset
Data Transfer
x = 7...0, depending on PEC channel number
Figure 5-5 PEC Pointer Address Handling
The 24-bit destination address is stored in the register DSTPx (lower 16 bits of address)
and in the low byte of register PECSEGx (highest 8 address bits). Only the lower 16 bits
of the PEC address pointers (segment offset) can be modified (incremented) by the PEC
transfer mechanism. The highest 8 bits, which represent the segment number, are not
modified by hardware. Therefore, the PEC pointers may be incremented within the
address space of one segment and may not cross the segment border. If the offset
address pointer gets the ‘FFFF_H’ value in the case of byte transfers (BWT = 1) or ‘FFFE_H’
in the case of word transfers (BWT = 0), the next increment will be disregarded. The
address register will keep one of these maximum values and no overflow will happen.
The described behavior protects the memory from unintentional overwriting. No explicit
error event is generated by the system in case of address pointer(s) saturation;
therefore, it is the user’s responsibility to prevent this condition.
Note: PEC data transfers do not use the data page pointers DPP3...DPP0.
Note: If a word data transfer is selected for a specific PEC channel (BWT = 0), the
respective source and destination pointers must both contain a valid word address
User Manual
5-146
V 1.7, 2001-01