C166SV2 Datasheet, PDF (29/438 Pages) Infineon Technologies AG – 16-Bit Microcontroller

User Manual
C166S V2
Central Processing Unit
Field
IP
0
Bits
[15:1]
[0]
Type Description
h
Specifies the intra segment offset from which the
current instruction is to be fetched. IP refers to the
current segment <SEGNR>.
-
IP is always word-aligned
The Code Segment Pointer CSP
This non-bit addressable register selects the code segment being used at run-time to
access instructions. The lower 8 bits of register CSP select one of up 256 segments of
64 Kilobytes each, while the higher 8 bits are reserved for future use. The reset value is
specified by the contents of the VECSEG register (Section 5.1.4).
CSP
Code Segment Pointer
SFR
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000000
rrrrrrrr
SEGNR
rh
Field
SEGNR
Bits Type Description
[7:0] rh
Specifies the code segment from which the current
instruction is to be fetched.
The actual code memory address is generated by direct extension of the 16-bit contents
of the IP register by the lower byte of the CSP register as shown in the figure below. The
CSP register can be only read and may not be written by data operations.
There are two modes: segmented and non-segmented. The mode is selected with the
SGTDIS bit in the CPUCON1 register. After reset, the segmented mode is selected.
CPUCON1
CPU Control Register 1
SFR
Reset Value: 0000_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
0
0
0
0
0
0
0
VECSC
WDT
CTL
SGT INT
DIS SCXT
BP
ZCJ
rrrrrrrrr
rw
rw rw rw rw rw
Note: For a summary of the CPUCON1 register, please refer to Section 2.3.6.
User Manual
2-29
V 1.7, 2001-01