C166SV2 Datasheet, PDF (248/438 Pages) Infineon Technologies AG – 16-Bit Microcontroller

User Manual
C166S V2
Detailed Instruction Description
DIVU
Group
16-by-16 Unsigned Division
Arithmetic Instructions
Syntax
DIVU op1
Source Operand(s)
op1 → WORD
MDL → WORD
DIVU
Destination Operand(s) MD → DOUBLEWORD
Operation
(MDL) ← (MDL) / (op1)
(MDH) ← (MDL) mod (op1)
Description
Performs an unsigned 16-bit by 16-bit division of the low order word stored in the MD
register by the source word operand op1. The unsigned quotient is then stored in the
low order word of the MD register (MDL) and the remainder is stored in the high order
word of the MD register (MDH).
CPU Flags
E
Z
V
C
N
0
*
*
0
*
E Always cleared.
Z Set if quotient, stored in the MDL register, equals zero. Cleared
otherwise. Undefined if the V flag is set.
V Set if the divisor op1 was zero.
C Always cleared.
N Set if the most significant bit of the quotient, stored in the MDL register, is
set. Cleared otherwise. Undefined if the V flag is set.
Encoding
Mnemonic
DIVU
Rw_n
Format
5B nn
Bytes
2
User Manual
8-248
V 1.7, 2001-01