TC1920 Datasheet, PDF (35/78 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1920
Preliminary
Serial Data Link Module (J1850)
Figure 11 shows a global view of the functional blocks of the J1850 interface.
C lock
C on tro l
f_SDLM
Address
Decoder
SDLM
M odule
(K e rn e l)
RXD
TXD
Port
C on tro l
RXJ1850
TXJ1850
Interrupt
C on tro l
MCB04550
Figure 11 General Block Diagram of the SDLM Interface
The J1850 module communicates with the external world via two I/O lines, the J1850
bus. The RXD line is the receive data input signal and TXD is the transmit data output
signal. The Serial Data Link Module provides serial communication to a J1850 based
serial bus. J1850 bus transceivers have to be implemented externally in a system. The
J1850 module is conform to the SAE Class B J1850 specification and compatible to
class 2 protocol.
General SDLM Features:
• Compliant to SAE Class B J1850 specification
• Full support of GM class 2 protocol
• Variable Pulse Width (VPW) format with 10.4 kBaud
• High speed receive/transmit 4x mode with 41.6 kBaud
• Digital noise filter
• Power save mode and automatic wake up upon bus activity
• Support of single byte headers or consolidated headers
• CRC generation & check
• Support of block mode for receive and transmit
Data Link Operation Features:
• 11 bytes transmit buffer
• Double buffered 11 bytes receive buffer
• Support of In-frame response (IFR) types 1,2,3
• Advanced interrupt handling for RX, TX and error conditions
• All interrupt sources can be enabled/disabled individually
• Support of automatic IFR for types 1,2 for three byte consolidated headers
Data Sheet
31
V 1.3, 2003-10