TC1920 Datasheet, PDF (24/78 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

Preliminary
Peripheral Control Processor (PCP)
Code
M em ory
PCODE
Param eter
M em ory
PRAM
TC1920
PCP
Processor
C o re
F P I-In te rfa c e
PCP Service
Req. Nodes
PSRNs
PCP Interrupt
C ontrol Unit
PICU
FPI Bus
PCP Interrupt
Arbitration Bus
CPU Interrupt
Arbitration Bus
MCB04784_mod
Figure 6 PCP block diagram
The PCP is designed to work in partnership with a host CPU and performs many of the
tasks that would conventionally be performed by CPU interrupt service routines or a
DMA controller. The PCP off-loads the host CPU from most of the time critical interrupts,
easing the implementation of systems based on operating systems.
In principle the PCP may be considered to be a conventional processor which only
executes code in response to interrupt service requests (i.e. has no processing which is
not at interrupt level). It has an architecture which efficiently supports DMA type of bus
transactions to / from arbitrary devices and memory addresses and also some
reasonable computational capabilities. Whenever the PCP responds to a PCP interrupt
request (which has a specific interrupt priority level) it will use a register set ("context")
specific to that individual interrupt level and will also generally execute code which is also
specific to that interrupt level. For this reason the term "Channel" will be used throughout
the remainder of this document to refer to all PCP resources associated with a particular
PCP interrupt level.
The architecture is flexible enough to allow the implementation of a subset of the
commands/instructions as a simple DMA controller.
The PCP has a Harvard architecture (i.e. separate code and data memory spaces). Any
FPI bus master (including the PCP itself) can access both PCP code (PCODE) and data
(PRAM) memory via the FPI bus.
Data Sheet
20
V 1.3, 2003-10