TC1920 Datasheet, PDF (22/78 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1920
Preliminary
External Bus Interface (EBU_LMB)
EBU_LMB is connected to the Local Memory Bus (LMB) of the TC1920 and also to the
FPI Bus. EBU_LMB is always a slave on the LMB and a master/slave on the FPI bus.
Any LMB masters thus can access external memories or devices through EBU_LMB.
Currently the maximum length of the bursts are according to the size of program and
data cache lines, i.e. 8 x 32-bit words. Single transfers (non-burst) are supported for 8-
bit, 16-bit and 32-bit wide access.
EBU_LMB
LMB Bus 64-bit
XBC
DME
SDRAM
Buffer
S lo w e r
D e v ic e s
50 MHz
FPI Bus 32-bit
XMI
External Bus Unit
External
M aster
EBUL3045_L
Figure 4 EBU_LMB block diagram
Features supported in EBU_LMB:
• Local Memory Bus (LMB 64-bit) support.
• External bus frequency: LMB frequency = 1:1 or 1:2 or 1:4.
• Highly programmable access parameters.
• Intel-style and Motorola-style peripheral/device support.
• SDRAM support (burst access, multibanking, precharge, refresh).
• 16- and 32-bit SDRAM data bus and support of 64, 128 and 256MBit devices.
• Burst flash support.
• Multiplexed access (address & data on the same bus) when SDRAM is not present on
the External Bus.
• Data Buffering: Code Prefetch Buffer, Read/Write Buffer.
• External master arbitration (compatible to C166 and other TriCore devices).
• 8 programmable address regions (1 dedicated for emulator).
• Little-endian and Big-endian support.
• CSGLB signal, dedicated pin, bit programmable to combine one or more CS lines, for
buffer control.
• RMW signal reflecting a read-modify-write action.
• Signal for controlling data flow of slow-memory buffer.
• Slave unit for external (off-chip) master to access devices on the FPI bus.
• Master unit for FPI master to access external (off-chip) devices.
• Data Mover Engine.
Data Sheet
18
V 1.3, 2003-10