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TC1920 Datasheet, PDF (25/78 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller | |||
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TC1920
Preliminary
FPI Bus
The Flexible Peripheral Interconnect Bus is designed with the requirements of high-
performance Systems-on-Chip in mind.
Key Features:
⢠Core independent
⢠Multi-master capability
⢠Demultiplexed operation
⢠Clock synchronous
⢠Peak transfer rate of up to 200 MBytes/s (@ 50 MHz bus clock)
⢠Address and data bus scalable (32 bit address bus, 32 bit data bus )
⢠8-/16- and 32 bit data transfers
⢠Broad range of transfer types from single to multiple data transfers
⢠Burst transfer capability
⢠EMI and power consumption minimized
LMB-Bus
The Local Memory Bus is a synchronous, pipelined, split bus with variable block size
transfer support. All signals relate to the positive clock edge.
The protocol supports 8,16,32 & 64 bits single beat transactions and variable length 64
bits block transfers.
Key Features:
The LMB provides the following features:
⢠Optimized for high speed and high performance
⢠32 bit address, 64 bit data busses
⢠Central simple per cycle arbitration
⢠Slave controlled wait state insertion
⢠Address pipelining (max. depth - 2)
⢠Split transactions
⢠Variable block length - 2, 4 or 8 beats of 64 bit data
Data Sheet
21
V 1.3, 2003-10
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