TC1920 Datasheet, PDF (19/78 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1920
Preliminary
System Architecture and Control
32-Bit TriCore CPU
• 32-bit architecture with 4-GByte unified data, program and input/output address space
• Fast automatic context-switch
• Dual 16 x 16 Multiply-accumulate (MAC) unit
• Saturating integer arithmetic
• Register based design with multiple variable register banks
• Bit handling
• Packed data operations
• Zero overhead loop
• Precise exceptions
• Flexible power management
Instruction Set with High Efficiency:
• 16/32-bit instructions for reduced code size
• Little endian byte ordering with support for big and little endian byte ordering at bus
interface
• Boolean, array of bits, character, signed and unsigned integer, integer with saturation,
signed fraction, double word integers and IEEE-754 single precision floating-point
data types
• Bit, 8-bit byte, 16-bit half word, 32-bit word and 64-bit double word data formats
• Powerful instruction set
• Flexible and efficient addressing mode for high code density
On-chip Code Memories
PMU Scratch-Pad SRAM (CSRAM):
The PMU memory consists of 24-KByte Code Scratchpad RAM (CSRAM) and 8-KByte
Instruction Cache (ICACHE).
Address range of the CSRAM:
• D400 0000_H - D400 5FFF_H
Boot ROM (BROM):
The TC1920 contains 32 KByte of Boot ROM memory, which can be used for device
operating mode initialization routines, bootstrap loader support or test functions.
The address range of the Boot ROM is:
• DFFF 8000_H – DFFF FFFF_H
Data Sheet
15
V 1.3, 2003-10