TC1920 Datasheet, PDF (26/78 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

Preliminary
On-Chip Debug System (OCDS)
The TC1920 architecture is supporting OCDS level 1 and 2.
Level
1
2
Run Time
Control
Yes
Yes
System access via
JTAG
Trace bus
Yes
No
Yes
Yes
TC1920
Basic PC trace
No
Yes
Table 2
Core-related and System Control Modules
Module
Address Range I/O Lines
Interrupt
Nodes
TriCore CPU
Slave Registers (CPS)
Memory Management¹⁾
Unit (MMU)
F7E0 FF00_H -
F7E0 FFFF_H
F7E1 8000_H -
F7E1 80FF_H
Segment Protection
Registers¹⁾
F7E1 C000_H -
F7E1 C0FF_H
Core Debug¹⁾
F7E1 FD00_H -
(Core OCDS)
F7E1 FDFF_H
TriCore CPU¹⁾
SFR, GPR
F7E1 FE00_H -
F7E1 FFFF_H
Program Memory Unit²⁾ F87F FD00_H -
(PMU)
F87F FDFF_H
Data Memory Unit²⁾
(DMU)
F87F FC00_H -
F87F FCFF_H
Peripheral Control
Processor (PCP)
F000 3F00_H -
F000 3FFF_H
External Bus Unit
(EBU)
F800 0000_H -
F800 03FF_H
System Control Unit
(SCU)
F000 0000_H -
F000 00FF_H
-
CPU_SRC0..3
CPU_SRCSB
-
-
-
-
-
-
-
-
-
-
-
-
-
PCP_SRC0..11
AD[31:0], A[23:0], -
27 control lines
4 XTAL, PORST,
HRST, 8 EXIN, NMI,
4 test, CLKOUT,
BYPASS
EXI_SRC0..4
NMI³⁾
FPI Bus Control Unit F000 0200_H -
-
(BCU)
F000 02FF_H
BCU_SRC
Data Sheet
22
V 1.3, 2003-10