TLE6270R Datasheet, PDF (27/35 Pages) Infineon Technologies AG – Quad Low Side Injector Driver

TLE6270R
Quad Low Side Injector Driver
Electrical Characteristics
6.7
SPI Timings
Electrical Characteristics: SPI Timings (see Figure 17), Load capacitor at SDO = 100 pF
V_CC = 4.5 V to 5.5 V, T_CASE = -40 °C to +125 °C, all voltages with respect to ground, positive current flowing into
pin (unless otherwise specified)
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min. Typ. Max.
6.7.1
6.7.2
6.7.3
6.7.4
Clock frequency (50% duty cycle)
Minimum time CLK = HIGH
Minimum time CLK = LOW
Propagation delay CLK to data at
SDO valid
f_CLK
t_CLH
t_CLL
t_PCLD
–
–
100 –
100 –
–
–
6.7.5 NCS = LOW to data at SDO valid t_CSDV
–
–
6.7.6 CLK low before NCS low
t_SCLCH
100
–
(setup time CLK to NCS change
H/L)
3
MHz –
–
ns
–
–
ns
–
100 ns
1)
100 ns
1)
–
ns
–
6.7.7 CLK change L/H after NCS = low t_HCLCL 100 –
–
ns
–
6.7.8 SDI input setup time
t_SCLD
20
–
–
ns
–
(CLK change H/L after SDI data
valid)
6.7.9 SDI input hold time
t_HCLD
20
–
–
ns
–
(SDI data hold after CLK change
H/L)
6.7.10 CLK low before NCS high
t_SCLCL
150
–
6.7.11 CLK high after NCS high
t_HCLCH
150
–
6.7.12 NCS L/H to output data float
t_PCHDZ
–
–
6.7.13 Capacitance at SDI, SDO, CLK, C_x
NCS
–
–
6.7.14 NCS filter time
t_fNCS
10
–
(pulses ≤ t_fNCS will be ignored)
1) Not subject to production test, specified by design
–
ns
–
–
ns
–
100 ns
1)
15
pF
1)
Ceramic Capacitor
40
ns
1)
NCS
CLK
SDO
SDI
tsclch
thclcl
tclh
tcll
tcsdv
tpcld
FSL
D0-OUT
tscld
thcld
D0-IN
Figure 17 SPI Timings
D1-IN
tsclcl
thclch
tpchdz
D7-OUT
D7-IN
Data Sheet
27
V1.3, 2008-12-23