TLE6270R Datasheet, PDF (19/35 Pages) Infineon Technologies AG – Quad Low Side Injector Driver

TLE6270R
Quad Low Side Injector Driver
Functional Description
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB MSB
LSB
t1 time
000: default value = 192 µs
LSB = 32µs
111 = 416 µs
t2 time
00000 : default value = 0µs
LSB = 2µs
111 = 62µs
Figure 15 Input Coder
Table 4 describes the time coding:
Table 4 Time Coding
D7
D6
D5
D4
D3
D2
D1
D0
Time
X
X
X
X
X
0
0
0
t₁ = 192 µs
X
X
X
X
X
0
0
1
t₁ = 224 µs
…
…
X
X
X
X
X
1
1
1
t₁ = 416 µs
0
0
0
0
0
X
X
X
t₂ = 0 µs
0
0
0
0
1
X
X
X
t₂ = 2 µs
…
…
1
1
1
1
1
X
X
X
t₂ = 62 µs
Shift Register
The serial output of the diagnostic shift register is SDO. The serial input is SDI.
With the H/L change on NCS the first bit of the diagnostic shift register is transmitted to the SDO output.
The CLK pin clocks the diagnostic shift register. New SDO data will appear on every CLK’s rising edge and new
SDI data will be latched into the shift register on every CLK’s falling edge.
With the first positive pulse of the CLK the failure register will be cleared by FR_CLEAR.
There is no bus collision at a small spike at the NCS. The CLK is always LOW, while the NCS signal is changing.
SPI Control
The SPI control block monitors the data transfer from failure register to shift register and clear these register.
This is done with the FR_SR_TRANS and FR_CLEAR signals as described in the following diagram:
Data Sheet
19
V1.3, 2008-12-23