TLE8209-2 Datasheet, PDF (26/41 Pages) Infineon Technologies AG – SPI Programmable H-Bridge

TLE8209-2
SPI Interface
9
SPI Interface
The serial SPI interface establishes a communication link between TLE8209-2 and the systems microcontroller.
The TLE8209-2 always operates in slave mode whereas the controller provides the master function. The
maximum baud rate is 2 MBaud.
By applying an active slave select signal at SS the TLE8209-2 is selected by the SPI-master. SI is the data input
(Slave In), SO the data output (Slave Out). Via SCK (Serial Clock Input) the SPI-clock is provided by the master.
In case of inactive slave select signal (High) the data output SO goes into tristate.
The first two bits of an instruction may be used to establish an extended device-addressing. This gives the
opportunity to operate up to 4 Slave-devices sharing one common SS signal from the Master-Unit (see Figure 17).
SS
SCK
SI
SO
DIS
ABE
shift-register
OR
8
DIA_REG
Reset
SPI-Control:
-> state machine
-> clock counter
-> instruction recognition
8
Diagnostics
Figure 15 SPI Block Diagram
9.1
General SPI Characteristics
1. During active reset conditions the SPI is driven into its default state. The output SO is set to high impedance
(tristate). When reset becomes inactive, the state machine enters into a wait state for the next instruction.
2. If the slave select signal at SS is inactive (high), the state machine is forced to wait for the following instruction.
3. During active (low) state of the select signal SS the falling edge of the serial clock signal SCK will be used to
latch the input data at SI. Output data at SO are driven with the rising edge of SCK. Further processing of the
data according to the instruction (i.e. modification of internal registers) will be triggered by the rising edge of
the SS signal.
4. In order to establish the option of extended addressing the upper two bits of the instruction byte (i.e. the first
two SI bits of a frame) are reserved to send a chip address. To avoid a bus conflict the output SO will remain
tristate during the addressing phase of a frame (i.e. until the address bits are recognized as a valid chip
Data Sheet
26
Rev. 1.4, 2014-10-28