TLI5012BE1000_15 Datasheet, PDF (24/37 Pages) Infineon Technologies AG – GMR-Based Angle Sensor

TLI5012B E1000
Specification
4.3.6 Clock Supply (CLK Timing Definition)
The internal clock supply of the TLI5012B E1000 is subject to production-specific variations, which have to be
considered for all timing specifications.
Table 4-11 Internal clock timing specification
Parameter
Symbol
Values
Unit
Min. Typ. Max.
Digital clock
f_DIG
Internal oscillator frequency
f_CLK
22.3 24
3.7 4.0
26.3 MHz
4.4 MHz
Note / Test Condition
4.3.6.1 External clock operation
In order to fix the IC timing and synchronize the TLI5012B E1000 with other ICs in a system, it can be switched to
operate with an external clock signal supplied to the IFC pin. The clock input signal must fulfill certain
requirements:
• The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse
width and must be spike-filtered.
• The duty cycle factor should typically be 50%, but it can vary between 30% and 70%.
• The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is
generated automatically and the sensor restarts with the internal clock. This is indicated by the S_RST, and
CLK_SEL bits, and additionally by the Safety Word (see Chapter 4.4.2.2).
tCLKh
tCLK
tCLKl
V_H
V_L
t
Figure 4-6 External CLK timing definition
Table 4-12 External Clock Specification
Parameter
Symbol
Values
Unit
Min. Typ. Max.
Input frequency
f_CLK
3.7 4.0
CLK duty cycle¹⁾²⁾
CLK_DUTY
30 50
CLK rise time
t_CLKr
CLK fall time
t_CLKf
1) Minimum duty cycle factor: t_CLKh(min) / t_CLK with t_CLK= 1 / f_CLK
2) Maximum duty cycle factor: t_CLKh(max) / t_CLK with t_CLK= 1 / f_CLK
4.4 MHz
70 %
30 ns
30 ns
Note / Test Condition
From V_L to V_H
From V_H to V_L
Data Sheet
24
Rev. 1.1, 2015-09