ICS9FG108 Datasheet, PDF (9/19 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4 CPU, PCI-Express & SATA Clocks

ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: PLL Frequency Control Register
Byte 10 Pin #
Name
Control Function
Bit 7
-
PLL N Div8
N Divider Prog bit 8
Bit 6
-
PLL N Div9
N Divider Prog bit 9
Bit 5
-
PLL M Div5
Bit 4
-
PLL M Div4
Bit 3
-
PLL M Div3
M Divider Programming
Bit 2
-
PLL M Div2
bit (5:0)
Bit 1
-
PLL M Div1
Bit 0
-
PLL M Div0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
The decimal representation of M
and N Divider in Byte 11 and 12
will configure the PLL VCO
frequency. Default at power up =
latch-in or Byte 0 Rom table.
VCO Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
PWD
X
X
X
X
X
X
X
X
SMBus Table: PLL Frequency Control Register
Byte 11 Pin #
Name
Control Function
Bit 7
-
PLL N Div7
Bit 6
-
PLL N Div6
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
PLL N Div5
PLL N Div4
PLL N Div3
PLL N Div2
N Divider Programming
Byte11 bit(7:0) and Byte10
bit(7:6)
Bit 1
-
PLL N Div1
Bit 0
-
PLL N Div0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
The decimal representation of M
and N Divider in Byte 11 and 12
will configure the PLL VCO
frequency. Default at power up =
latch-in or Byte 0 Rom table.
VCO Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
PWD
X
X
X
X
X
X
X
X
SMBus Table: PLL Spread Spectrum Control Register
Byte 12 Pin #
Name
Control Function
Bit 7
-
PLL SSP7
Bit 6
-
PLL SSP6
Bit 5
-
Bit 4
-
Bit 3
-
PLL SSP5
PLL SSP4
PLL SSP3
Spread Spectrum
Programming bit(7:0)
Bit 2
-
PLL SSP2
Bit 1
-
PLL SSP1
Bit 0
-
PLL SSP0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
These Spread Spectrum
bits in Byte 13 and 14 will
program the spread
pecentage of PLL
PWD
X
X
X
X
X
X
X
X
SMBus Table: PLL Spread Spectrum Control Register
Byte 13 Pin #
Name
Control Function
Type
Bit 7
-
Reserved
Bit 6
-
PLL SSP14
RW
Bit 5
-
PLL SSP13
RW
Bit 4
-
Bit 3
-
Bit 2
-
PLL SSP12
Spread Spectrum
RW
PLL SSP11
Programming bit(14:8)
RW
PLL SSP10
RW
Bit 1
-
PLL SSP9
RW
Bit 0
-
PLL SSP8
RW
0
1
These Spread Spectrum
bits in Byte 13 and 14 will
program the spread
pecentage of PLL
PWD
0
X
X
X
X
X
X
X
IDT^TM/ICS^TM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
9
ICS9FG108 REV G 04/06/07