ICS9FG108 Datasheet, PDF (8/19 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4 CPU, PCI-Express & SATA Clocks

ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Byte Count Register
Byte 6
Pin #
Name
Bit 7
-
BC7
Bit 6
-
BC6
Bit 5
-
BC5
Bit 4
-
BC4
Bit 3
-
BC3
Bit 2
-
BC2
Bit 1
-
BC1
Bit 0
-
BC0
Control Function
Writing to this register will
configure how many bytes
will be read back, default is
07 = 7 bytes.
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBus Table: Reserved Register
Byte 7
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
SMBus Table: Reserved Register
Byte 8
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
SMBus Table: M/N Programming Enable
Byte 9
Pin #
Name
Control Function
Bit 7
-
Bit 6
-
Bit 5
5
M/N_EN
OE_Polarity
REFOUT_En
PLL M/N Programming
Enable
Select Polarity of OE inputs
Enables/Disables REF
Bit 4
Reserved
Bit 3
Reserved
Bit 2
Reserved
Bit 1
Reserved
Bit 0
Reserved
Type
RW
RW
RW
0
-
-
-
-
-
-
-
-
0
0
0
Disable
OE#
Disable
1
PWD
-
0
-
0
-
0
-
0
-
0
-
1
-
1
-
1
1
PWD
X
X
X
X
X
X
X
X
1
PWD
X
X
X
X
X
X
X
X
1
Enable
OE
Enable
PWD
0
1
1
0
0
0
0
0
IDT^TM/ICS^TM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
8
ICS9FG108 REV G 04/06/07