ICS9FG108 Datasheet, PDF (7/19 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4 CPU, PCI-Express & SATA Clocks

ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Frequency Select Readback Register
Byte 3
Pin #
Name
Control Function
Bit 7
27
SEL14M_25M#¹
(FS3)
State of pin 27
Bit 6
6
FS2¹
State of pin 6
Bit 5
44
FS1¹
State of pin 44
Bit 4
45
FS0¹
State of pin 45
Bit 3
26
SPREAD¹
State of pin 26
Bit 2
Reserved
Bit 1
Reserved
Bit 0
Reserved
Type
R
R
R
R
R
R
R
R
0
1
PWD
See Frequency
Selection Table, Page 1
Off
On
Reserved
Reserved
Reserved
Pin 27
Pin 6
Pin 44
Pin 45
Pin 26
X
X
X
Notes:
1. These bits reflect the state of the corresponding pins, regardless of whether software
programming is enabled or not.
SMBus Table: Vendor & Revision ID Register
Byte 4
Pin #
Name
Control Function
Type
0
Bit 7
-
RID3
R
-
Bit 6
-
Bit 5
-
RID2
RID1
REVISION ID
R
R
-
-
Bit 4
-
RID0
R
-
Bit 3
-
VID3
R
-
Bit 2
-
Bit 1
-
VID2
VID1
VENDOR ID
R
-
R
-
Bit 0
-
VID0
R
-
1
PWD
-
X
-
X
-
X
-
X
-
0
-
0
-
0
-
1
SMBus Table: DEVICE ID
Byte 5
Pin #
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Name
DEVID7
DEVID6
DEVID5
DEVID4
DEVID3
DEVID2
DEVID1
DEVID0
Control Function
Device ID = 08 hex
Type
R
R
R
R
R
R
R
R
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWD
0
0
0
0
1
0
0
0
IDT^TM/ICS^TM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
7
ICS9FG108 REV G 04/06/07