ICS9FG108 Datasheet, PDF (2/19 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4 CPU, PCI-Express & SATA Clocks

ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Configuration
XIN/CLKIN 1
X2 2
VDD 3
GND 4
REFOUT 5
**FS2 6
**OE_7 7
DIF_7 8
DIF_7# 9
VDD 10
DIF_6 11
DIF_6# 12
*OE_6 13
VDD 14
GND 15
*OE_5 16
DIF_5 17
DIF_5# 18
VDD 19
DIF_4 20
DIF_4# 21
**OE_4 22
SDATA 23
SCLK 24
48 VDDA
47 GNDA
46 IREF
45 **FS0
44 **FS1
43 **OE_0
42 DIF_0
41 DIF_0#
40 VDD
39 DIF_1
38 DIF_1#
37 *OE_1
36 VDD
35 GND
34 *OE_2
33 DIF_2
32 DIF_2#
31 VDD
30 DIF_3
29 DIF_3#
28 **OE_3
27 *SEL14M_25M#
26 **SPREAD
25 DIF_STOP#
* indicates internal 120K pull up
** indicates internal 120K pull down
48-pin SSOP & TSSOP
Functionality Table
Frequency Select Table
SEL14M_25M#
(FS3)
FS2 FS1 FS0 OUTPUT(MHz)
0
000
100.00
0
001
125.00
0
010
133.33
0
011
166.67
0
100
200.00
0
101
266.66
0
110
333.33
0
111
400.00
1
000
100.00
1
001
125.00
1
010
133.33
1
011
166.67
1
100
200.00
1
101
266.66
1
110
333.33
1
111
400.00
Power Groups
Pin Number
VDD
GND
3
4
10,14,19,31,36,40 15,35
N/A
47
48
47
Description
REFOUT, Digital Inputs, SMBus
DIF Outputs
IREF
Analog VDD & GND for PLL Core
IDT^TM/ICS^TM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
2
ICS9FG108 REV G 04/06/07