ICS9FG108 Datasheet, PDF (3/19 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4 CPU, PCI-Express & SATA Clocks

ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN NAME
XIN/CLKIN
X2
VDD
GND
REFOUT
**FS2
**OE_7
DIF_7
DIF_7#
VDD
DIF_6
DIF_6#
*OE_6
VDD
GND
*OE_5
DIF_5
DIF_5#
VDD
DIF_4
DIF_4#
**OE_4
SDATA
SCLK
PIN TYPE
IN
OUT
PWR
PWR
OUT
IN
IN
OUT
OUT
PWR
OUT
OUT
IN
PWR
PWR
IN
OUT
OUT
PWR
OUT
OUT
IN
I/O
IN
DESCRIPTION
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
Ground pin.
Reference Clock output
Frequency select pin.
Active high input for enabling output 7.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
Power supply, nominal 3.3V
Ground pin.
Active high input for enabling output 5.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active high input for enabling output 4.
0 = tri-state outputs, 1= enable outputs
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Note:
Pin names followed by '**' have 120 Kohm pull DOWN resistors
Pin names followed by '*' have 120 Kohm pull UP resistors
IDT^TM/ICS^TM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
3
ICS9FG108 REV G 04/06/07