ICS9FG108 Datasheet, PDF (12/19 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4 CPU, PCI-Express & SATA Clocks

ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Absolute Max
Symbol
Parameter
VDD_A
3.3V Core Supply Voltage
VDD_In 3.3V Logic Input Supply Voltage
Ts
Tambient
Tcase
ESD prot
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
GND - 0.5
-65
0
2000
Max
V_DD + 0.5V
V_DD + 0.5V
150
70
115
Units
V
V
°_C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Input High Voltage
V_IH
3.3 V +/-5%
2
V_DD + 0.3 V
Input Low Voltage
Input High Current
Input Low Current
V_IL
3.3 V +/-5%
V_SS -
0.3
I_IH
V_IN = V_DD
-5
I_IL1
V_IN = 0 V; Inputs with no pull- _-5
up resistors
I_IL2
V_IN = 0 V; Inputs with pull-up _-200
resistors
0.8 V
5
uA
uA
uA
I_DD3.3OP
Operating Supply Current
Full Active, C_L = Full load;
f = 400 MHz
Full Active, C_L = Full load;
f = 100 MHz
215 250 mA
1
180 200 mA
1
I_DD3.3STOP
All outputs stopped driven
All outputs stopped Hi-Z
180 200 mA
1
51 60 mA
1
Input Frequency³
F_i
Pin Inductance¹
L_pin
V_DD = 3.3 V
14
25 MHz 3
7
nH
1
Input/Output
Capacitance¹
C_IN
C_OUT
Logic Inputs
1.5
Output pin capacitance
5
pF
1
6
pF
1
Clk Stabilization^1,2
T_STAB
From V_DD Power-Up and after
input clock stabilization to 1st
1 1.8 ms 1,2
clock
Modulation Frequency
f_MOD
Triangular Modulation
30
33 kHz
1
DIF output enable
t_DIFOE
DIF output enable after
DIF_Stop# de-assertion
9.8 15 ns
1
Input Rise and Fall times t_R/t_F
20% to 80% of VDD
5
ns
1
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3 _{Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25}
MHz to meet
IDT^TM/ICS^TM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108 REV G 04/06/07
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