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ICS9ERS3125 Datasheet, PDF (9/22 Pages) Integrated Device Technology – Embedded 56-pin Industrial Temperature Range CK505 Compatible Clock
ICS9ERS3125
Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
Datasheet
Electrical Characteristics - 27MHz_Spread / 27MHz_NonSpread
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
Long Accuracy
ppm
see Tperiod min-max values
-50
50
Clock period
Tperiod
27.000MHz output nominal
Output High Voltage
VOH
IOH = -1 mA
Output Low Voltage
VOL
IOL = 1 mA
Output High Current
IOH
V OH @MIN = 1.0 V
VOH@MAX = 3.135 V
Output Low Current
IOL
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Edge Rate
tslewr/f
Rising/Falling edge rate
Rise Time
tr1
VOL = 0.4 V, VOH = 2.4 V
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
Duty Cycle
dt1
VT = 1.5 V
tltj
Long Term (10us), VT = 1.5 V
Jitter
tjpk-pk
VT = 1.5 V
tj c y c -c y c
VT = 1.5 V
*TA = -40 - 85°C; Supply Voltage VDD = 3.3 V +/-5%, Rs = 39Ω, CL = 5pF
37.0352
2.4
-29
29
1
0.5
0.5
45
-200
37.0389
0.55
-23
27
4
2
2
55
800
200
200
UNITS
ppm
ns
V
V
mA
mA
mA
mA
V/ns
ns
ns
%
ps
ps
ps
Electrical Characteristics - Differential Jitter Parameters
PARAMETER
Symbol
Conditions
Min
Jitter, Phase
tjphasePLL
tjphaseLo
PCIe Gen 1
PCIe Gen 2
10kHz < f < 1.5MHz
tjphaseHigh
PCIe Gen 2
1.5MHz < f < Nyquist (50MHz)
*TA = -40 - 85°C; Supply Voltage VDD = 3.3 V +/-5%, Rs= 0Ω, CL = 2pF
TYP
Max
Units
86 ps (p-p)
3
ps
(RMS)
3.1
ps
(RMS)
Notes on Electrical Characteristics:
1Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through Vswing centered around differential zero
3 Vxabs is defined as the voltage where CLK = CLK#
4 Only applies to the differential rising edge (CLK rising and CLK# falling)
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK
and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.
The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.
6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
7 Operation under these conditions is neither implied, nor guaranteed.
8 Maximum input voltage is not to exceed maximum VDD
9 See PCI Clock-to-Clock Delay Figure
10 At nominal voltage and temperature
11 See http://www.pcisig.com for complete specs
Notes
1,6
6
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes
1,11
1,11
1,11
IDTTM/ICSTM Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
9
1612—08/19/09