ICS9ERS3125 Datasheet, PDF (1/22 Pages) Integrated Device Technology – Embedded 56-pin Industrial Temperature Range CK505 Compatible Clock

DATASHEET
Embedded 56-pin Industrial Temperature
Range CK505 Compatible Clock
ICS9ERS3125
Recommended Application:
Industrial temperature CK505-compatible clock
Output Features:
• 2 - CPU differential push-pull pairs
• 4 - SRC differential push-pull pairs
• 1 - CPU/SRC selectable differential push-pull pair
• 1 - DOT96/SRC selectable differential push-pull pair
• 1 - 27M/SRC/SE selectable pair
• 1 - SRC/SATA selectable differential push-pull pair
• 5 - PCI, 33MHz
• 1 - PCI_F 33MHz free running
• 1 - USB, 48MHz
• 1 - REF, 14.31818MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 100ppm frequency accuracy on all outputs
Pin Configuration
Features/Benefits:
• Fully integrated Vreg
• Differential outputs have integrated series resistors to give
ZO = 50 Ohms
• Supports spread spectrum modulation, 0 to -0.5% down
spread
• Supports CPU clks up to 400MHz
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Table 1: CPU Frequency Select Table
FSLC²
B0b7
FSLB¹
B0b6
FSLA¹
B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
0
0
0
266.66
0
0
1
133.33
0
1
0
200.00
0
1
1
166.66 100.00 33.33 14.318 48.00 96.00
1
0
0
333.33
1
0
1
100.00
1
1
0
400.00
1
1
1
Reserved
1. FS_LA and FS_LB are low-threshold inputs.Please see V_{IL_FS} and V_{IH_FS} specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_LC is a three-level input. Please see the V_{IL_FS} and V_{IH_FS}
specifications in the Input/Supply/Common Output Parameters Table for correct values.
56 55 54 53 52 51 50 49 48 47 46 45 44 43
X2 1
42 GNDSRC
X1 2
41 VDDSRC
VDDREF 3
40 PCI_STOP#
REF0/FSLC/TEST_SEL 4
39 CPU_STOP#
SDATA 5
38 VDDSRC_IO
SCLK 6
37 SRCT11/CR#_H
PCI0/CR#_A 7
VDDPCI 8
9ERS3125
36 SRCC11/CR#_G
35 GNDSRC
PCI1/CR#_B 9
34 SRCC4
PCI2/TME 10
33 SRCT4
PCI3 11
32 VDDSRCI/O
PCI4/27_SEL 12
31 SRCC3/CR#_D
PCI_F5/ITP_EN 13
30 SRCT3/CR#_C
GNDPCI 14
29 GNDSRC
15 16 17 18 19 20 21 22 23 24 25 26 27 28
27_SEL
0 (B1b7=1)
1 (B1b7=0)
pin19
DOT96T
SRCT0
pin20
DOT96C
SRCC0
27_SEL
0
1
pin23
LCDT_SS
27FIX
pin24
LCDC_SS
27SS
NOTE: Pin 23/24 defaults to a different spread domain than
SRC without BIOS intervention.
CR_# Control Table PCIEX pair control
CR_#A
SRC0 or SRC2
CR_#B
SRC1 or SRC4
CR_#C
SRC0 or SRC2
CR_#D
SRC1 or SRC4
CR_#E
SRC6
CR_#F
SRC8
CR_#G
N/A
CR_#H
N/A
CR_# SEL
0
1
SRC0
SRC2
SRC1
SRC4
SRC0
SRC2
SRC1
SRC4
-
-
-
-
-
-
-
-
56-pin MLF
8x8mm body
IDT^TM/ICS^TM Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
1
1612—08/19/09