ICS9ERS3125 Datasheet, PDF (4/22 Pages) Integrated Device Technology – Embedded 56-pin Industrial Temperature Range CK505 Compatible Clock

ICS9ERS3125
Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
Datasheet
Pin Description (continued)
37 SRCT11/CR#_H
38 VDDSRC_IO
39 CPU_STOP#
40 PCI_STOP#
41 VDDSRC
42 GNDSRC
43 SRCC7CR#_E
I/O
PWR
IN
IN
PWR
PWR
I/O
44 SRCT7/CR#_F
I/O
45 CPUC2_ITP/SRCC8
46 CPUT2_ITP/SRCT8
47 VDDCPUI/O
48 CPUC1_F
49 CPUT1_F
50 GNDCPU
51 CPUC0
52 CPUT0
53 VDDCPU
54 CK_PWRGD/PD#
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
IN
SRC11 true or Clock Request control H for SRC11 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request control of
SRC3 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair
must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC3 pair using
byte 6, bit 4 of SMBus configuration space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC3.
NOTE: SRC10 NOT AVAILABLE ON 9LRS3125
Power supply for SRC outputs. 1.05 to 3.3V +/-5%.
Stops all CPU Clocks, except those set to be free running clocks.
In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values
Stops all PCI/SRC Clocks, except those set to be free running clocks.
In AMT mode, this pin is a clock input which times the FSC, FSB, FSA bits shifted in on
CPU_STOP#..
3.3V Power supply for SRC PLL and Logic
Ground for SRC clocks
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request control of
SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair
must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using
byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR# E controls SRC6.
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of
SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair
must first be disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using
byte 6, bit 6 of SMBus configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR# F controls SRC8.
Complement clock of low power differential CPU2/Complement clock of differential SRC pair.
The function of this pin is determined by the latched input value on pin 14, PCIF5/ITP_EN on
powerup. The function is as follows:
Pin 14 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The function of
this pin is determined by the latched input value on pin 14, PCIF5/ITP_EN on powerup. The
function is as follows:
Pin 14 latched input Value
0 = SRC8
1 = ITP
Power supply for CPU outputs. 1.05 to 3.3V +/-5%.
Complement clock of low power differential CPU clock pair. This clock will be free-running
during iAMT.
True clock of low power differential CPU clock pair. This clock will be free-running during
iAMT.
Ground Pin for CPU Outputs
Complement clock of low power differential CPU clock pair.
True clock of low power differential CPU clock pair.
3.3V Power Supply for CPU.
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
55 FSLB/TEST_MODE
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for
IN Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and
REF/N divider mode while in test mode. Refer to Test Clarification Table.
56 GNDREF
PWR Ground pin for crystal oscillator circuit
IDT^TM/ICS^TM Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
1612—08/19/09
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