ICS9ERS3125 Datasheet, PDF (15/22 Pages) Integrated Device Technology – Embedded 56-pin Industrial Temperature Range CK505 Compatible Clock

ICS9ERS3125
Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
Datasheet
Byte 0 FS Readback & PLL Selection Register
Bit
Name
Description
7
FSLC
CPU Freq. Sel. Bit (Most Significant)
6
FSLB
CPU Freq. Sel. Bit
5
FSLA
CPU Freq. Sel. Bit (Least Significant)
Type
R
R
R
0
1
See Table 1 : CPU Frequency Select Table
4
iAMT_EN
Set via SMBus or dynamically by CK505 if detects dynamic M1 R
Legacy Mode
iAMT Enabled
3
Reserved
2
SRC_Main_SEL
Select source for SRC Main
RW SRC Main = PLL5
SRC Main = PLL2
1
SATA_SEL
Select source for SATA clock
RW SATA = SRC_Main
SATA = PLL3
1 = on Power Down de-assert return to last known state
0 = clear all SMBus configurations as if cold power-on and go to
Configuration Not
0
PD_Restore
latches open state
RW
Saved
Configuration Saved
This bit is ignored and treated at '1' if device is in iAMT mode.
Default
Latch
Latch
Latch
iAMT power
on status
1
0
0
1
Byte 1 DOT96 Select & PLL3 Quick Config Register,
Note 1 : When 27_Select pin = 0, B1b7 Default = 1; When 27_Select pin = 1, Default = 0
Bit
Name
7
SRC0_SEL
6
PLL5_SSC_SEL
5
PLL2_SSC SEL
4
PLL1_CF3
3
PLL1_CF2
2
PLL1_CF1
1
PLL1_CF0
0
PCI_SEL
Description
Select SRC0 or DOT96
Select 0.5% down or center SSC
Select 0.5% center or down SSC
PLL1 Quick Config Bit 3
PLL1 Quick Config Bit 2
PLL1 Quick Config Bit 1
PLL1 Quick Config Bit 0
PCI_SEL
Type
0
1
RW
SRC0
DOT96
RW
Down spread
Center spread
RW
Down
Center
RW _{See Table 2: pin 27FIX/LCDT/SRCT_LR1/SE1,}
RW _{27SS/LCDC/SRCC_LR1/SE2 Configuration}
RW
RW
Only applies if Byte 0, bit 2 = 0.
RW
PCI from PLL5
PCI from SRC_MAIN
Default
Note 1
0
0
0
0
1
0
1
Byte 2 Single Ended Output Enable Register
Bit
Name
7
REF_OE
6
USB_OE
5
PCIF5_OE
4
PCI4_OE
3
PCI3_OE
2
PCI2_OE
1
PCI1_OE
0
PCI0_OE
Description
Output enable for USB
Output enable for USB
Output enable for PCI5
Output enable for PCI4
Output enable for PCI3
Output enable for PCI2
Output enable for PCI1
Output enable for PCI0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Default
1
1
1
1
1
1
1
1
Byte 3 SRC Output Enable Register
Bit
Name
7
SRC11_OE
6
5
4
SRC8/ITP_OE
3
SRC7_OE
2
SRC6_OE
1
0
SRC4_OE
Description
Output enable for SRC11
Reserved
Reserved
Output enable for SRC8 or ITP
Output enable for SRC7
Output enable for SRC6
Reserved
Output enable for SRC4
Type
RW
0
Output Disabled
RW Output Disabled
RW Output Disabled
RW Output Disabled
RW Output Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Default
1
1
1
1
1
1
1
1
Byte 4 SRC/CPU/DOT Output Enable & Spread Spectrum Disable Register
Bit
Name
Description
7
SRC3_OE
Output enable for SRC3
6
SATA/SRC2_OE
Output enable for SATA/SRC2
5
SRC1_OE
Output enable for SRC1
4
SRC0/DOT96_OE
3
CPU1_OE
Output enable for SRC0/DOT96
Output enable for CPU1
2
CPU0_OE
Output enable for CPU0
1
PLL5_SSC_ON
Enable PLL5's spread modulation
0
PLL2_SSC_ON
Enable PLL2's spread modulation
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Spread Disabled
Spread Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Spread Enabled
Spread Enabled
Default
1
1
1
1
1
1
1
1
IDT^TM/ICS^TM Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
15
1612—08/19/09