ICS9ERS3125 Datasheet, PDF (16/22 Pages) Integrated Device Technology – Embedded 56-pin Industrial Temperature Range CK505 Compatible Clock

ICS9ERS3125
Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
Datasheet
Byte 5 Clock Request Enable/Configuration Register
Bit
Name
Description
7
CR#_A_EN
Enable CR#_A (clk req) for SRC0 or SRC2
6
CR#_A_SEL
Sets CR#_A to control either SRC0 or SRC2
5
CR#_B_EN
Enable CR#_B (clk req) for SRC1 or SRC4
4
CR#_B_SEL
Sets CR#_B to control either SRC1 or SRC4
3
CR#_C_EN
Enable CR#_C (clk req) for SRC0 or SRC2
2
CR#_C_SEL
Sets CR#_C to control either SRC0 or SRC2
1
CR#_D_EN
Enable CR#_D (clk req) for SRC1 or SRC4
0
CR#_D_SEL
Sets CR#_D to control either SRC1 or SRC4
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable CR#_A
CR#_A -> SRC0
Disable CR#_B
CR#_B -> SRC1
Disable CR#_C
CR#_C -> SRC0
Disable CR#_D
CR#_D -> SRC1
1
Enable CR#_A
CR#_A -> SRC2
Enable CR#_B
CR#_B -> SRC4
Enable CR#_C
CR#_C -> SRC2
Enable CR#_D
CR#_D -> SRC4
Default
0
0
0
0
0
0
0
0
Byte 6 Clock Request Enable/Configuration Register
Bit
Name
Description
7
CR#_E_EN
6
CR#_F_EN
5
4
3
2
Enable CR#_E (clk req) for SRC6
Enable CR#_F (clk req) for SRC8
Reserved
Reserved
Reserved
Reserved
1
LCD/SRC1_STP_CRTL•
If set, LCD_SS/SRC1 stops with PCI_STOP#
0
SRC0_STP_CRTL
If set, SRC0 stop with PCI_STOP#
Type
RW
RW
RW
RW
0
Disable CR#_E
Disable CR#_F
Free Running
Free Running
1
Enable CR#_E
Enable CR#_F
Stops with
PCI_STOP# assertion
Stops with
PCI_STOP# assertion
Default
0
0
0
0
0
0
0
0
Byte 7 Vendor ID/ Revision ID Register
Bit
Name
7
Rev Code Bit 3
6
Rev Code Bit 2
5
Rev Code Bit 1
4
Rev Code Bit 0
3
Vendor ID bit 3
2
Vendor ID bit 2
1
Vendor ID bit 1
0
Vendor ID bit 0
Description
Revision ID
Vendor ID
ICS is 0001, binary
Type
R
R
R
R
R
R
R
R
0
1
Vendor specific
Default
0
0
0
1
0
0
0
1
Byte 8 Device ID & Output Enable Register
Bit
Name
Description
Type
7
Device_ID3
R
6
Device_ID2
Table of Device identifier codes, used for differentiating between R
5
Device_ID1
CK505 package options, etc.
R
4
Device_ID0
3
2
R
Reserved
Reserved
1
27MHz_nonSS/SE1_OE
0
27MHz_SS/SE2_OE
Output enable for SE1
RW
Output enable for SE2
RW
0
1
See Device ID Table 4
Disabled
Disabled
Enabled
Enabled
Default (MLF)
0
0
0
0
0
0
1
1
Byte 9 Test and Output Control Register
Bit
Name
Description
7
PCIF5 STOP EN
Allows control of PCIF5 with assertion of PCI_STOP#
6
TME_Readback
5
4
Test Mode Select
3
Test Mode Entry
2
CPU IO_VOUT2
1
CPU IO_VOUT1
0
CPU IO_VOUT0
Truested Mode Enable (TME) strap status
Reserved
Allows test select, ignores REF/FSC/TestSel
Allows entry into test mode, ignores FSB/TestMode
CPU IO Output Voltage Select (Most Significant Bit)
CPU IO Output Voltage Select
CPU IO Output Voltage Select (Least Significant Bit)
Type
RW
R
RW
RW
RW
RW
RW
0
Free running
normal operation
1
Stops with
PCI_STOP# assertion
no overclocking
Outputs HI-Z
Normal operation
Outputs = REF/N
Test mode
See Table 3: V_IO Selection
(Default is 0.8V)
Default
0
TME latch
1
0
0
1
0
1
IDT^TM/ICS^TM Embedded 56-Pin Industrial Temperature Range CK505 Compatible Clock
16
1612—08/19/09