ICS87972I-147 Datasheet, PDF (9/17 Pages) Integrated Device Technology – Fully integrated PLL

ICS87972I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Parameter Measurement Information
1.65V±5%
V_DD,
V_DDA,
V_DDO
LVCMOS
GND
-1.65V±5%
SCOPE
Qx
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
Qx
Qy
t sk(o)
Output Skew
QA[0:3],
QB[0:3],
QC[0:3],
QSYNC,
QFB
V
DDO
2
V
DDO
2
tcycle n
➤
tcycle n+1
| | tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
V
DDO
2
➤
QA[0:3],
QB[0:3],
QC[0:3],
QSYNC,
QFB
t _PW
V
DDO
2
t
PERIOD
odc = ^{t PW} x 100%
t _PERIOD
Cycle-to-Cycle Jitter
Output Duty Cycle/Pulse Width Period
CLK0,
V_DD
CLK1
2
V_DD
EXT_FB
2
➤_t(Ø)
t(Ø) mean = Static Phase Offset
Where t(Ø) is any random sample, and t(Ø) mean is the
average of the sampled cycles measured on controlled edges
Static Phase Offset
QA[0:3],
2V
QB[0:3],
QC[0:3],
QSYNC, _0.8V
QFB
t_R
Output Rise/Fall Time
2V
0.8V
t_F
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
9
ICS87972DYI-147 REV. A JUNE 5, 2008