ICS87972I-147 Datasheet, PDF (8/17 Pages) Integrated Device Technology – Fully integrated PLL

ICS87972I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Table 5. Input Frequency Characteristics, V_DD = V_DDA = V_DDO = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
CLK0, CLK1; NOTE 1
F_IN
Input Frequency XTAL1, XTAL
12
FRZ_CLK
Maximum
150
40
20
Units
MHz
MHz
MHz
NOTE 1: Input frequency depends on the feedback divide ratio to ensure "clock * feedback divide" is in the VCO range of 240MHz to
500MHz.
Table 6. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum Typical Maximum
Fundamental
12
40
50
7
Units
MHz
Ω
pF
AC Electrical Characteristics
Table 7. AC Characteristics, V_DD = V_DDA = V_DDO = 3.3V ± 5%, T_A = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum
÷2
÷4
f_MAX
Output Frequency
÷6
÷8
t(Ø)
Static Phase
CLK0
Offset; NOTE 1 _CLK1
QFB ÷ 8,
-10
In Frequency = 50MHz
-65
tsk(o)
Output Skew; NOTE 2, 3
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 3
All Banks ÷ 4
f_VCO
t_LOCK
t_R / t_F
odc
PLL VCO Lock Range
PLL Lock Time; NOTE 4
Output Rise/Fall Time
Output Duty Cycle
240
0.8V to 2V
0.15
45
t_PZL, t_PZH
t_PLZL, t_PHZ
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
Typical
145
90
Maximum
150
125
83.33
62.5
300
245
200
55
500
10
0.7
55
10
8
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
MHz
ms
ns
%
ns
ns
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked
and the input reference frequency is stable.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
8
ICS87972DYI-147 REV. A JUNE 5, 2008