ICS87972I-147 Datasheet, PDF (10/17 Pages) Integrated Device Technology – Fully integrated PLL

ICS87972I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform-
ance, power supply isolation is required. The ICS87972I-147
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V_DD, V_DDA and V_DDO
should be individually connected to the power supply plane
through vias, and 0.01µF bypass capacitors should be used for
each pin. Figure 2 illustrates this for a generic V_DD pin and also
shows that V_DDA requires that an additional 10Ω resistor along with
a 10µF bypass capacitor be connected to the V_DDA pin.
3.3V
V_DD
.01µF _10Ω
V_DDA
.01µF
10µF
Figure 2. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
CLK Inputs
For applications not requiring the use of the clock input, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK to ground.
LVCMOS Control Pins
All control pins have internal pull-ups; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
Outputs:
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no
trace attached.
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
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ICS87972DYI-147 REV. A JUNE 5, 2008