ICS87972I-147 Datasheet, PDF (4/17 Pages) Integrated Device Technology – Fully integrated PLL

ICS87972I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Table 1. Pin Descriptions
Number
1
2
3
4
5,
26,
27
6
7
8
9, 10
11,
12
13
14
15, 24, 30,
35, 39, 47,
51
16, 18,
21, 23
17, 22, 33,
37, 45, 49
19,
20
25
28
29
31
32, 34,
36, 38
40,
41
42,
43
44, 46
48, 50
52
Name
GNDI
nMR/OE
FRZ_CLK
FRZ_DATA
FSEL_FB2,
FSEL_FB1,
FSEL_FB0
PLL_SEL
REF_SEL
CLK_SEL
CLK0, CLK1
XTAL_1,
XTAL_2
V_DDA
INV_CLK
GNDO
QC3, QC2,
QC1, QC0
V_DDO
FSEL_C1,
FSEL_C0
QYSNC
V_DD
QFB
EXT_FB
QB3, QB2,
QB1, QB0
FSEL_B1,
FSEL_B0
FSEL_A1,
FSEL_A0
QA3, QA2,
QA1, QA0
VCO_SEL
Type
Power
Input Pullup
Input
Input
Pullup
Pullup
Input Pullup
Input Pullup
Input Pullup
Input
Input
Input
Power
Input
Pullup
Pullup
Pullup
Power
Output
Power
Input Pullup
Output
Power
Output
Input
Output
Pullup
Input Pullup
Input Pullup
Output
Input Pullup
Description
Power supply ground.
Master reset and output enable. When HIGH, enables the outputs.
When LOW, resets the outputs to Hi-Z and resets output divide circuitry.
Enables and disables all outputs. LVCMOS / LVTTL interface levels.
Clock input for freeze circuitry. LVCMOS / LVTTL interface levels.
Configuration data input for freeze circuitry. LVCMOS / LVTTL interface levels.
Select pins control Feedback Divide value. LVCMOS / LVTTL interface levels.
See Table 3B.
Selects between the PLL and reference clocks as the input to the output dividers.
When HIGH, selects PLL. When LOW, bypasses the PLL and reference clocks.
LVCMOS / LVTTL interface levels.
Selects between crystal and reference clock. When LOW, selects CLK0 or CLK1.
When HIGH, selects crystal inputs. LVCMOS / LVTTL interface levels.
Clock select input. When LOW, selects CLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
Single-ended reference clock inputs. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_1 is the input. XTAL_2 is the output.
Analog supply pin.
Inverted clock select for QC2 and QC3 outputs. LVCMOS / LVTTL interface levels.
Power supply ground.
Single-ended Bank C clock outputs. LVCMOS/ LVTTL interface levels.
Output power supply pins.
Select pins for Bank C outputs. LVCMOS / LVTTL interface levels. See Table 3A.
Synchronization output for Bank A and Bank C. Refer to Figure 1, Timing Diagrams.
LVCMOS / LVTTL interface levels.
Power supply pin.
Single-ended feedback clock output. LVCMOS / LVTTL interface levels.
External feedback. LVCMOS / LVTTL interface levels.
Single-ended Bank B clock outputs. LVCMOS/ LVTTL interface levels.
Select pins for Bank B outputs. LVCMOS / LVTTL interface levels. See Table 3A.
Select pins for Bank A outputs. LVCMOS / LVTTL interface levels. See Table 3A.
Single-ended Bank A clock outputs. LVCMOS/ LVTTL interface levels.
Selects VCO. When HIGH, selects VCO ÷ 1. When LOW, selects VCO ÷ 2.
LVCMOS / LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
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ICS87972DYI-147 REV. A JUNE 5, 2008