ICS87972I-147 Datasheet, PDF (5/17 Pages) Integrated Device Technology – Fully integrated PLL

ICS87972I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLUP
C_PD
R_OUT
Parameter
Input Capacitance
Input Pullup Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
V_DD, V_DDA, V_DDO = 3.465V
Minimum
5
Typical
4
51
7
Maximum
18
12
Units
pF
kΩ
pF
Ω
Function Tables
Table 3A. Output Bank Configuration Select Function Table
Inputs
Outputs
Inputs
FSEL_A1 FSEL_A0
QA
FSEL_B1 FSEL_B0
0
0
÷4
0
0
0
1
÷6
0
1
1
0
÷8
1
0
1
1
÷12
1
1
Outputs
QB
÷4
÷6
÷8
÷10
Inputs
FSEL_C1 FSEL_C0
0
0
0
1
1
0
1
1
Outputs
QC
÷2
÷4
÷6
÷8
Table 3B. Feedback Configuration Select Function Table
Inputs
Outputs
FSEL_FB2 FSEL_FB1 FSEL_FB0
QFB
0
0
0
÷4
0
0
1
÷6
0
1
0
÷8
0
1
1
÷10
1
0
0
÷8
1
0
1
÷12
1
1
0
÷16
1
1
1
÷20
Table 3C. Control Input Select Function Table
Control Pin
Logic 0
Logic 1
VCO_SEL
VCO/2
VCO
REF_SEL
CLK0 or CLK1
XTAL
CLK_SEL
CLK0
CLK1
PLL_SEL
BYPASS PLL
Enable PLL
nMR/OE
Master Reset/Output Hi-Z
Enable Outputs
INV_CLK
Non-Inverted QC2, QC3
Inverted QC2, QC3
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
5
ICS87972DYI-147 REV. A JUNE 5, 2008