ICS87972I-147 Datasheet, PDF (3/17 Pages) Integrated Device Technology – Fully integrated PLL

ICS87972I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Simplified Block Diagram
XTAL1
XTAL2
CLK0 ^Pullup
CLK1 ^Pullup
CLK_SEL ^Pullup
REF_SEL ^Pullup
EXT_FB ^Pullup
1
0
0
1
PLL
VCO RANGE
240MHz - 500MHz
VCO_SEL ^Pullup
PLL_SEL ^Pullup
nMR/OE
0
÷2
0
1
÷1
1
FSEL_A[0:1]
2
FSEL_
A1 A0 QAx
0 0 ÷4
0 1 ÷6
1 0 ÷8
1 1 ÷12
FSEL_B[0:1]
2
FSEL_
B1 B0 QBx
0 0 ÷4
0 1 ÷6
1 0 ÷8
1 1 ÷10
FRZ_CLK ^Pullup
FRZ_DATA ^Pullup
FSEL_C[0:1]
2
FSEL_
C1 C0 QCx
0 0 ÷2
0 1 ÷4
1 0 ÷6
0
1 1 ÷8
1
INV_CLK
FSEL_FB[0:2]
3
FSEL_
FB2 FB1 FB0 QFB
0 0 0 ÷4
0 0 1 ÷6
0 1 0 ÷8
0 1 1 ÷10
1 0 0 ÷8
1 0 1 ÷12
1 1 0 ÷16
1 1 1 ÷20
OUTPUT DISABLE
CIRCUITRY
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
QFB
QSYNC
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
3
ICS87972DYI-147 REV. A JUNE 5, 2008