ICS87972I-147 Datasheet, PDF (2/17 Pages) Integrated Device Technology – Fully integrated PLL

ICS87972I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Block Diagram
XTAL1
XTAL2
VCO_SEL ^Pullup
PLL_SEL ^Pullup
REF_SEL ^Pullup
1
0
CLK0 ^Pullup ₀
CLK1 ^Pullup ₁
CLK_SEL ^Pullup
EXT_FB ^Pullup
PHASE
DETECTOR
0
VCO
1
LPF
FSEL_FB2 ^Pullup
nMR/OE ^Pullup
POWER-ON
RESET
FSEL_A[0:1] ^Pullup
FSEL_B[0:1] ^Pullup
FSEL_C[0:1] ^Pullup
FSEL_FB[0:2] ^Pullup
FRZ_CLK ^Pullup
FRZ_DATA ^Pullup
INV_CLK ^Pullup
÷4, ÷6, ÷8, ÷12
÷4, ÷6, ÷8, ÷10
÷2, ÷4, ÷6, ÷8
2
÷4, ÷6, ÷8, ÷10
2
2
SYNC PULSE
3
DATA GENERATOR
0
÷2 1
OUTPUT DISABLE
12
CIRCUITRY
DQ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
DQ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
DQ
DQ
DQ
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
DQ
SYNC
FRZ
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
QFB
QSYNC
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
2
ICS87972DYI-147 REV. A JUNE 5, 2008