ICS87972I-147 Datasheet, PDF (11/17 Pages) Integrated Device Technology – Fully integrated PLL

ICS87972I-147
LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Crystal Input Interface
The ICS87972I-147 has been characterized with 18 pF parallel
resonant crystals. External capacitors are not required for this
crystal interface. While layout the PC board, it is recommended to
have spare footprints capacitor C1 and C2. If required, the spare
C1 and C2 footprints can be used for fine tuned further for more
accurate frequency. The possible C1 and C2 value are ranged from
2pF – 25pF. The suggest footprint size is 0402 or 0603.
X1
18pF Parallel Crystal
C1
Spare
XTAL_IN
C2
Spare
XTAL_OUT
Figure 3. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 4. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VCC
VCC
R1
Ro
Rs
50Ω
0.1µf
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 4. General Diagram for LVCMOS Driver to XTAL Input Interface
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
11
ICS87972DYI-147 REV. A JUNE 5, 2008